The provided V1 tarball (see: modules page) contains a presumed-working (for the same subset of MIPS instructions as V0) FDEMW pipelined processor with:
Always-Predict-Not-Taken branch prediction
Hazard detection and branch resolution in D
Non-coherent IMEM and DMEM memories (stores to DMEM will not appear in IMEM)
The IMEM and DMEM memory modules currently always supply/accept the requested operations. However, they also each provide a READY signal that is false the first time the 4-byte block containing the specified address is accessed and true for any subsequent access to that same block.
Your task: Change the stall / NOP insertion logic to accommodate the existence of potential 1-cycle “stalls” in one or both of the IMEM/DMEM.
Goal: This project serves as direct preparation for the cache integration in the final project, where the I$ and D$ will have misses. While the mechanism and timing for determining hits/misses/evictions for cache interactions will be different, the pipeline interface for the final project will be nearly identical to the one implemented here.
What to submit:
Your Vivado project directory, as a gzipped tarball.
https://drive.google.com/file/d/1LHWP7cl9natS-lktp…https://drive.google.com/file/d/1te2yCT54WW4CtrB8U…here are two links of supporting videos, one of them is pretty long so I will extend the deadline
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