CMPEN 331 Pennsylvania State University Emulating DIVU with MIPS instructions Worksheet

Description

Programming assignment 0Using the provided framework .asm file (divu-student.asm, linked via canvas modules) and the MARS MIPS simulator (linked under support documentation), you will implement the body of a function, in MIPS, that provides the same functionality as the DIVU instruction, i.e. computing both the quotient and remainder for unsigned integer division, without using the DIVU instruction itself.Use the provided slides in the week 5 deck on how to perform unsigned binary division as a guide to implementing your solution. You are free to consult any third party reference on how to perform general binary unsigned division, but you must write (and provide comments for) your own MIPS code solution within the provided framework.Your code must work within MARS. Links to the MARS documentation and a link to the MARS JAR file itself are available in the Supporting Documentation module. The provided framework will print the results of both the DIVU instruction and your emulated DIVU behavior to the MARS console, so you can directly check if your solution works.To turn in:1 File: Your modified divu-student.asm : Please read the comments within the file for what you are required to modify and what you are forbidden from modifying in the framework code.This assignment is not intended to be particularly difficult (a fairly direct translation of the flowchart from the slides into MIPS instructions is an efficient solution, and the recitation on Friday will cover one way to emulate a 64-bit register with 32-bit registers) — it is, however, intended to force you to use the MARS simulator and write some MIPS assembly code. Please consider starting on this assignment early enough to encounter any issues that you have in using the tools in time to receive assistance.MARS websit:http://courses.missouristate.edu/KenVollmar/MARS/

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MIPs opcode map (COD Figure A.10.2).
Left Shift and Subtract Division Hardware
divisor
subtract
32-bit ALU
dividend
remainder
quotient
ShiftReg64
Division supplement.1
shift
left
Control
Left Shift and Subtract Restoring Division
Hardware (4-bit) [ example: 6 divided by 2]
0010
=2
(1 1 1 0 = – 2)
divisor
subtract
4-bit ALU
dividend
remainder
quotient
ShiftReg8
Iter 1:sub
Iter 2:sub
Iter 3:sub
Iter 4:sub
0000
0000
1110
0000
0001
1111
0001
0011
0001
0010
0000
0110
1100
1100
1100
1000
1000
1000
0000
0001
0010
0011
shift
left
Control
=6
Init Done
rem neg, so Q3 bit = 0
restore remainder
rem neg, so Q2 bit = 0
restore remainder
rem pos, so Q1 bit = 1
rem pos, so Q0 bit = 1
= 3 with 0 remainder
Division supplement.2
Previous Example, Step by Step
State of ShiftReg8 =
{rem, quot}
How we got to that state
0000 0110
initialize remainder | quotient with 0 | dividend
0000 1100
shift left 1 (these two steps collectively represent initialization)
1110 1100
trial subtract (remainder – divisor, 0000 – 0010 is 1110)
set the lsb of quotient to 0
0000 1100
trial subtract result is negative, restore the previous remainder
0001 1000
shift left
1111 1000
trial subtract (0001 – 0010 is 1111)
set the lsb of quotient to 0
0001 1000
trial subtract result is negative, restore the previous remainder
0011 0000
shift left
0001 0001
trial subtract (0011 – 0010 is 0001)
set the lsb of quotient to 1
0010 0010
shift left
0000 0011
trial subtract (0010 – 0010 is 0000)
set the lsb of quotient to 1
lsb of quotient is set to complement of msb of trial subtract result
Division supplement.3
Non-restoring division

Don’t update the register if the result would be negative (so you don’t
have to restore it) …

HW way: Pre-compute both possible updates:
Possible update 1: subtract and shift, append 1
Possible update 2: just shift, append 0
Mux based on sign bit of subtraction output

SW way: Check and branch
shouldSubtract = divisor

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